1. Field of the Invention
This invention relates generally to the field of integrated circuit packaging.
2. Description of the Related Art
In the manufacture of integrated circuits, extremely fine circuits are photolithographically placed onto a chip, also called a die. The circuits on the chip terminate at conductive terminals on the face of the chip, which must be electrically connected to power and to other chips. For protection of the chip and ease of handling, the chips are bonded to a substrate and placed in a package having electrical connections ultimately leading to a conventional printed circuit board. One attractive means of connecting the conductive terminals on a chip is the technique where the terminals on the face of the chip are distributed over the face of the chip in a pattern of “C4” connections. These terminals are typically connected to a circuit substrate by conductive paste or solder.
In some integrated circuit packaging, the chip is mounted to the underside of a circuit substrate with its C4 connections facing the circuit substrate. Also, in some integrated circuit packaging applications, there are at least two integrated circuit chips having very high communication bandwidth or bitrate between them. For example, a high speed processor often requires a very high communication bandwidth with an associated memory chip. A cost-effective, high bandwidth interconnection between two (or more) devices can be made by stacking chips with the C4 patterns facing each other and electrically interconnecting them vertically using very short connections between the chips. This approach ensures a consistent, very short length interconnect between the chips which can enable extremely wide, high speed, low skew busses between the two chips.
Where two chips are stacked facing each other, an interposer, for example, an intermediate circuit layer, between the devices is usually necessary to efficiently distribute power to the devices and facilitate high yield assembly and test. Ideally, the interposer should be no thicker than required to adequately distribute power to the devices since the thickness of the interposer increases the interconnect length of the busses between the devices and effectively degrades the electrical performance of the interconnect. An advantageous interposer is fabricated as a lamination having a two metal layer (2 ML) bumped circuit layer with overlaying outer conductive layers bonded to the 2 ML circuit layer with an intervening layer of insulating adhesive.
Attachment of the chip on the underside of the interposer can pose a clearance difficulty. A typical BGA solder ball array may use solder balls in the range of 400 to 800 microns in diameter, more typically 400 to 600 microns. For example, the C4 connections of the chip on the lower side of the interposer may be attached with solder balls or paste that may have a thickness of approximately 100 microns and the chip itself may have a thickness in the range of approximately 350 microns. If it is desired to have an approximately 200 micron clearance between the chip and the bottom substrate of the package, it would be difficult or impossible to achieve the necessary clearance using a typical BGA solder ball array having solder balls in the range of 400 to 600 microns in diameter connected to the bottom of a circuit substrate, without thinning the inactive face of the chip.
To alleviate this clearance problem, taller, multi-component solder columns in large ceramic BGA (CBGA) package applications could be used. Taller columns are required in some applications to ensure the board level reliability due to the large mismatch between thermal expansion of the CBGA and the board on which it is mounted, which creates stress between the solder column and the connection pad at the point of connection. The stress on the interconnect is reduced as the height of these solder columns is increased. Although solder columns could be used to provide the necessary clearance for a chip mounted on the underside of the package as described above, this would add cost to the package and additionally may not be compatible with desired board-level assembly processes.